The present invention relates generally to phase locked loop (PLL) circuitry and in particular to a frequency agile PLL system which generates a clock signal that is synchronized to signal transitions occurring in a received data stream.
In a data communications system, multiple data processing systems transmit data to, and receive data from each other over a shared network. Generally, the network includes a number of interconnected nodes, each having a respective clock signal generator. The data transmitted by each node is synchronized to the clock signal provided by its clock signal generator.
In order to receive data, however, a node cannot use its own clock signal unless steps are taken to synchronize the incoming data stream with the local clock signal. If the receiving clock signal is not synchronized to the incoming data in both frequency and phase, the data may not be received properly.
Consider, for example, the data communications network shown in FIG. 1. In this FIGURE, three network transceivers, 110, 122 and 130 are connected in a daisy-chain configuration. The transceivers 110, 122 and 130 are coupled to respective host processors 116, 126 and 134. This may represent, for example, a portion of a ring data communications network. The transceivers 110, 122 and 130 have respective clock oscillators 112, 124 and 132, Which produce respective local clock signals used by the transceivers, and the host processors 116, 126 and 134 have respective clock oscillators 118, 128 and 136 Which produce the clock signals that are used by the host processors.
In normal operation, transceiver 110 receives and sends data over the network on behalf of the host processor 116. Data, destined for the host 116 which is received from the network by transceiver 110 is forwarded to the host processor 116 over the bidirectional data link DL. Data to be sent over the network from the host processor 116 to, for example, the host processor 126 is provided to the transceiver 110 via the data link DL.
If the host processor properly receives a message from the transceiver 110, it sends an acknowledgement (ACK) message back to the transceiver. It the message was not properly received, the host processor 116 sends a negative acknowledgement (NAK) message to the transceiver 110. The transmission link from the host 116 to the transceiver 110 uses the same scheme. When one of the processor 116 or transceiver 110 receives a NAK message, it retransmits the message. When the clock signals used by the host processor and transceiver are not aligned, a message may need to be transmitted several times before an ACK message is received.
Data sent between the transceivers and their respective host processors is encoded into packets according to a known protocol. The protocol includes a data formatting technique (e.g. NRZI encoding), which encodes the transmitting clock signal with the data. The protocol may also include a defined synchronizing signal which is sent to synchronize the receiver to the transmitter before data is sent.
In a typical network of the type shown in FIG. 1, the transceiver 110 sends data to the host, synchronous with its internal clock signal, over a dedicated signal path. The host includes a phase locked loop (PLL) 120 which recovers the clock signal that was used by the transceiver 110 to transmit the data. Using this recovered clock signal, the host processor decodes the data sent by the transceiver. The transceiver 110 decodes data received from the host 116 using a similar PLL 114 which recovers the clock signal that is encoded in the data by the host 116.
This configuration works well when the transmitting clock signals have fixed frequencies and the encoded data streams have frequent transitions. If a data formatting technique is selected which ensures frequent transitions in the data stream, then the loop time constant of the PLL may be selected to be relatively low and still maintain phase lock between the clock signals used by the host processor 116 and the network transceiver 110. Using a data encoding technique such as NRZI ensures that there will be relatively frequent transitions in the signal during most of the time data is transmitted. There will also be intervals, however, in which transitions are infrequent.
A synchronization system used with a data encoding technique in which intervals having infrequent transitions are a possibility may compensate for these intervals by increasing the loop time constant of the PLL's 114 and 120. Due to the relatively long time constant of the PLL's, however, data is usually transmitted across the data link at a single baud rate. This rate is determined when the network is configured based on the length and type of interconnecting cable as well as the capabilities of the transmitters and receivers at either end of the data link. Thus, the assignment of data transmission rates may involve considerable effort during the initial configuration of the network.
Generally, it is desirable to transmit data at the highest rate which is supported by the link. This rate depends on the kind and length of the link and on the environment in which it is used. If, for example, a twisted-pair data link is used in an environment which is intermittently subject to high levels of radio frequency interference (RFI), it may be desirable to reduce the data rate during intervals of high RFI to avoid data corruption. During intervals in which the RFI is absent or attenuated, it may be desirable to increase the data rate to improve system performance.
If the PLL's 114 and 120 of the system shown in FIG. 1 have relatively long loop time constants, they may require a relatively long initial synchronization time and a relatively long synchronization time after each change in frequency of the transmitting clock signal. No data may be transmitted during these synchronization intervals. On the other hand, if the PLL's 114 and 120 have relatively short loop time constants, the frequencies and phases of the transmitting clock signals may be initialized or changed relatively rapidly, but they may exhibit excessive drift when the data signals have long periods without transitions.
U.S. Pat. No. 4,554,659 to Blood et al. addresses this problem by treating the incoming data as an asynchronous signal. Each node includes a first-in-first-out (FIFO) memory which accepts data at one clock signal frequency and provides it at another.
U.S. Pat. No. 4,569,017 to Renner et al describes a synchronization circuit which periodically executes a predetermined set of instructions that cause the internal clocks of two data processing elements to coincide.